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1 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator december 2009 2009 integrated device technology, inc. dsc 7117/4 c idt5v9885c industrial temperature range 3.3v eeprom programmable clock generator the idt logo is a registered trademark of integrated device technology, inc. features: ? three internal plls ? internal non-volatile eeprom ? jtag and fast mode i 2 c serial interfaces ? input frequency ranges: 1mhz to 400mhz ? output frequency ranges: 4.9khz to 500mhz ? reference crystal input with programmable oscillator gain and programmable linear load capacitance ? crystal frequency range: 8mhz to 50mhz ? each pll has an 8-bit pre-scaler and a 12-bit feedback-divider ? 10-bit post-divider blocks ? fractional dividers ? two of the plls support spread spectrum generation capability ? i/o standards: ? outputs - 3.3v lvttl/ lvcmos, lvpecl, and lvds ? inputs - 3.3v lvttl/ lvcmos ? programmable slew rate control ? programmable loop bandwidth settings ? programmable output inversion to reduce bimodal jitter ? redundant clock inputs with glitchless auto and manual switchover options ? jtag boundary scan ? individual output enable/disable ? power-down mode ? 3.3v v dd ? available in tqfp and vfqfpn packages description: the idt5v9885c is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and networking applications. there are three internal plls, each individually programmable, allowing for three unique non-integer-related frequencies. the frequencies are generated from a single reference clock. the reference clock can come from one of the two redundant clock inputs. a glitchless automatic or manual switchover function allows any one of the redundant clocks to be selected during normal operation. the idt5v9885c can be programmed through the use of the i 2 c or jtag interfaces. the programming interface enables the device to be programmed when it is in normal operation or what is commonly known as in-system programmable. an internal eeprom allows the user to save and restore the configuration of the device without having to reprogram it on power-up. jtag boundary scan is also implemented. each of the three plls has an 8-bit pre-scaler and a 12-bit feedback divider. this allows the user to generate three unique non-integer-related frequencies. the pll loop bandwidth is programmable to allow the user to tailor the pll response to the application. for instance, the user can tune the pll parameters to minimize jitter generation or to maximize jitter attenuation. spread spectrum generation and fractional divides are allowed on two of the plls. there are 10-bit post dividers on five of the six output banks. two of the six output banks are configurable to be lvttl, lvpecl, or lvds. the other four output banks are lvttl. the outputs are connected to the plls via the switch matrix. the switch matrix allows the user to route the pll outputs to any output bank. this feature can be used to simplify and optimize the board layout. in addition, each output's slew rate and enable/disable function can be programmed.
2 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator functional block diagram eeprom control block for multi-purpose i/o, programming, features osc. pll 0 pll 1 pll 2 10-bit p2 divider 10-bit p6 divider 10-bit p3 divider 10-bit p4 divider 10-bit p5 divider xtalout xtalin/refin clkin shutdown/oe gin5/clk_sel i c/jtag 2 g i n 0 / s d a t / t d i g i n 1 / s c l k / t c l k g i n 2 / t m s g i n 3 / s u s p e n d g i n 4 / t r s t /2 /2 out1 out3 out4 out4 out5 out5 out2 out6 gout0/tdo/ loss_lock gout1/ loss_clkin (1) (1) (1) (1) /2 /2 /2 note: 1. out4 and out5 pairs can be configured to be lvds, lvpecl, or two single-ended lvttl outputs. as lvttl, out4 and out5 can be configured to be non-inverting.
3 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator pin configuration 31 10 o u t 4 30 29 28 27 26 25 11 12 13 14 15 16 g o u t 0 . t d o / l o s s _ l o c k o u t 2 s h u t d o w n / o e g i n 3 / s u s p e n d v d d o u t 4 o u t 6 o u t 5 o u t 5 v d d g n d g n d 32 9 v d d g n d g i n 4 / t r s t 1 2 3 4 5 6 7 8 clkin gnd gout1/loss_clkin xtalin/refin out1 v dd out3 xtalout 18 gnd 24 23 22 21 20 19 i c/jtag gin2/tms v dd gin1/sclk/tclk gin0/sda/tdi gin5/clk_sel 17 v dd 2 tqfp top view 27 26 25 24 23 22 g o u t 0 . t d o / l o s s _ l o c k o u t 2 s h u t d o w n / o e g i n 3 / s u s p e n d g n d 28 v d d g i n 4 / t r s t 8 o u t 4 9 1011121314 o u t 4 o u t 6 o u t 5 o u t 5 v d d g n d 1 2 3 4 5 6 7 clkin gnd gout1/loss_clkin xtalin/refin out1 out3 xtalout 21 20 19 18 17 16 i c/jtag gin2/tms v dd gin1/sclk/tclk gin0/sda/tdi gin5/clk_sel 15 v dd 2 gnd vfqfpn top view
4 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator pin description pf32 nl28 pin name pin# pin# i/o type description clkin 1 1 i lvttl input clock xtalin/refin 4 4 i lvttl crystal_in - reference crystal input or external reference clock input xtalout 5 5 o lvttl crystal_out -reference crystal feedback gin0/sdat/tdi 19 16 i lvttl (1,2) multi-purpose inputs. can be used for frequency control, sdat(i 2 c), or tdi(jtag). gin1/sclk/tck 20 17 i lvttl (1,2) multi-purpose inputs. can be used for frequency control, sclk(i 2 c), or tck(jtag). gin2/tms 24 21 i lvttl (1,2) multi-purpose inputs. can be used for frequency control or tms (jtag) gin3/suspend 27 23 i lvttl (1,2) multi-purpose inputs. can be used for frequency control or as a suspend mode control input (active high). gin4/trst 25 22 i lvttl (1,2) multi-purpose inputs. can be used for frequency control or trst (jtag) gin5/clk_sel 21 18 i lvttl (1,2) multi-purpose inputs. can be used for frequency control or input clock selector. shutdown/oe 28 24 i lvttl (1,2) enables/disables the outputs or powers down the chip. the sp bit (0x1c) controls the polarity of the signal to be either active high or low. (default is active high.) i 2 c/jtag 22 19 i 3-level (3) i 2 c (high) or mfc mode (mid) or jtag programming (low) out1 6 6 o lvttl configurable clock output 1. can also be used to buffer the reference clock. out2 29 25 o lvttl configurable clock output 2 out3 8 7 o lvttl configurable clock output 3 out4 10 8 o adjustable (4) configurable clock output 4, single-ended or differential when combined with out4 out4 11 9 o adjustable (4) configurable complementary clock output 4, single-ended or differential when combined with out4 out5 15 13 o adjustable (4) configurable clock output 5, single-ended or differential when combined with out5 out5 16 14 o adjustable (4) configurable complementary clock output 5, single-ended or differential when combined with out5 out6 13 11 o lvttl configurable clock output 6 gout0/tdo/loss_lock 31 27 o lvttl (1) multi-purpose output. can be programmed to use as pll lock signal, loss_lock or tdo in jtag mode gout1/loss_clkin 3 3 o lvttl multi-purpose output. can be programmed to use as loss_clkin v dd 7,12,17, 10,15,20 3.3v power supply 23,26,32 28 gnd 2,9,14, 2,12,26 ground 18,30 notes: 1. the jtag (tdo, tms, tclk, trst, and tdi) and i 2 c (sclk and sdat) signals share the same pins with gin signals. 2. weak internal 100k ? pull-down resistor. 3. 3-level inputs are static inputs and must be tied to v dd or gnd or left floating. these inputs are internally biased to v dd /2. they are not hot-insertable or over voltage tolerant. 4. outputs are user programmable to drive single-ended 3.3v lvttl, differential lvds, or differential lvpecl interface levels.
5 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator pll features and descriptions pll2 block diagram pll0 block diagram pll1 block diagram vco d0 divider m0 multiplier spread spectrum modulation vco d1 divider m1 multiplier spread spectrum modulation vco d2 divider m2 multiplier
6 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator spread spectrum pre-divider (d) values multiplier (m) values programmable loop bandwidth generation capability pll0 1 - 255 2 - 8190 yes yes pll1 1 - 255 2 - 8190 yes yes pll2 1 - 255 1 - 4095 yes no reference clock input pins and selection the 5v9885c supports up to two clock inputs. one of the clock inputs (xtalin/ refin) can be driven by either an external crystal or a reference clock. the second clock input (clkin) can only be driven from an external reference clock. either clock input can be set as a the primary clock. the primary clock designation is to establish which is the main reference clock to the plls. the non-primary clock is designated as the secondary clock in case the primary clock goes absent and a backup is needed. the primclk bit (0x34) determines which clock input will be the primary clock. when primclk bit is "0", it will select xtalin/refin as the primary, and when "1", it will select clkin as the primary. the two external reference clocks can be manually selected using the gin5/clk_sel pin, except in manual frequency control (mfc) mode 2, or via programming by hard wiring the clk_sel pin and toggling the primclk bit. for more details on the mfc modes, refer to the configuring multi-purpose i/os section. when clk_sel is low, the primary clock is selected and when high, the secondary clock is selected. the sm bits (0x34) must be set to "0x" for manual switchover which is detailed in switchover modes section. xtal load cap = 3.5pf + xtalcap[7:0] * 0.125pf (eq. 1) crystal input (xtalin/refin) the crystal oscillators should be fundamental mode quartz crystals: overtone crystals are not suitable. crystal frequency should be specified for parallel resonance with 50 ? maximum equivalent series resonance. when the xtalin/refin pin is driven by a crystal, it is important to set the internal oscillator inverter drive strength and internal tuning/load capacitor values correctly to achieve the best clock performance. these values are programmable through either i 2 c or jtag interface to allow for maximum compatibility with crystals from various manufacturers, processes, performances, and qualities. the internal load capacitors are true parallel-plate capacitors for ultra-linear performance. parallel-plate capacitors were chosen to reduce the frequency shift that occurs when non-linear load capacitance interacts with load, bias, supply, and temperature changes. external non-linear crystal load capacitors should not be used for applications that are sensitive to absolute frequency requirements. the value of the internal load capacitors are determined by xtalcap[7:0] bits, (0x07). the load capacitance can be set with a resolution of 0.125 pf for a total crystal load range of 3.5pf to 35.5pf. this value should be set to two times the crystal load capacitance value stated by the vendor, subtracting out board capacitance value. check with the vendor's crystal load capacitance specification for the exact setting to tune the internal load capacitor. the following equation governs how the total internal load capacitance is set. ex.: for crystal capacitance = 12pf for board capacitance = 3pf each leg xtalcap = 2x [12-3] = 18pf gin5/clk_sel selected clock input l primary h secondary parameter bits step min max units xtalcap 8 0.125 0 32 pf when using an external reference clock instead of a crystal on the xtal/ refin pin, the input load capacitors may be completely bypassed. this allows for the input frequency to be up to 200mhz. when using an external reference clock, the xtalout pin must be left floating, xtalcap must be programmed to the default value of "0", and crystal drive strength bit, xdrv (0x06), must be set to the default value of "11". clkin pin clkin pin is a regular clock input pin, and can be driven up to 400mhz. pre-scaler, feedback-divider, and post-divider each pll incorporates an 8-bit pre-scaler and a 12-bit feedback divider which allows the user to generate three unique non-integer-related frequencies. for output banks out2-out6, each bank has a 10-bit post-divider. the following equation governs how the frequency on output banks out2-6 is calculated. f out = f in * d (eq. 2) where f in is the reference frequency, m is the total feedback-divider value, d is the pre-scaler value, p is the total post-divider value, and f out is the resulting output bank frequency. the value 2 in the denominator is due to the divide- by-2 on each of the output banks out2-6. note that out1 does not have any type of post-divider. also, programming any of the dividers may cause glitches on the outputs. pre-scaler d[7:0] are the bits used to program the pre-scaler for each pll, d0 for pll0, d1 for pll1, and d2 for pll2. the pre-scalers divide down the reference clock with integer values ranging from 1 to 255. to maintain low jitter, the divided down clock must be higher than 400khz; it is best to use the smallest d divider value possible. if d is set to '0x00', then this will power down the pll and all the outputs associated with that pll. m p * 2 ( )
7 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator feedback-divider n[11:0] and a[3:0] are the bits used to program the feedback-divider for pll0 (n0 and a0) and pll1 (n1 and a1). if spread spec trum generation is enabled for either pll0 or pll1, then the ss_offset[5:0] bits (0x61, 0x69) would be factored into the overall feedback divider value. see the spread spectrum generation section for more details on how to configure pll0 and pll1 when spread spectrum is enabled. the two plls can also b e configured for fractional divide ratios. see fractional divider for more details. for pll2, only the n[11:0] bits (n2) are used to program its feedback divider and there is no spread spectrum generation and fractional divides capability. the12-bit feedback-divider integer values range from 1 to 4095. the following equations govern how the feedback divider value is set. note that the equations are different for pll0/pll1 and pll2 pll0 and pll1: m = 2*n[11:0] + a[3:0] + 1 + ss_offset[5:0] * 1/64 (eq. 3) m = 2*n[11:0] + a[3:0] + 1 (spread spectrum disabled) (eq. 4) a[3:0] = 0000 = -1 = 0001 = 1 = 0010 = 2 = 0011 = 3 . . . = 1111 = 15 note: a[3:0] < (n[11:0] - 5), must be met when using a. n cannot be programmed with a value of 4, 8, or 16 when using a. pll2: m = n[11:0] (eq. 5) the user can achieve an even or odd integer divide ratio for both pll0 and pll1 by setting the a[3:0] bits accordingly and disa bling the spread spectrum. a fractional divide can also be set for pll0 and pll1 by using the a[3:0] bits in conjunction with the ss_offset[5:0] bits, whi ch is detailed in the fractional divider section. note that the vco has a frequency range of 10mhz to 1200mhz. to maintain low jitter, it is best to maximize the vco frequency. for example, if the reference clock is 100mhz and a 200mhz clock is required, to achieve the best jitter performance, multiply the 100mhz b y 12 to get the vco running at the highest possible frequency of 1200mhz and then divide it down to get 200mhz. or if the reference clock is 25mhz and 20mhz is the required clock, multiply the 25mhz by 40 to get the vco running at 1000mhz and then divide it down to get 20mhz. if n is set to '0x00', the vco will sl ew to the minimum frequency. post-divider q[9:0] are the bits used to program the 10-bit post-dividers on output banks out2-6. out1 bank does not have a 10-bit post-div ider or any other post- divide along its path. the 10-bit post-dividers will divide down the output banks' frequency with integer values ranging from 1 to 1023. there is the option to choose between disabling the post-divider, utilizing a div/1, a div/2, or the 10-bit post-divider by usi ng the pm[1:0] bits. each bank, except for out1, has a set of pm bits. when disabling the post-divider, no clock will appear at the outputs, but will remain powered on. the values are listed in the table below. pm[1:0] p post-divider 00 disabled 01 div/1 10 div/2 11 q[9:0] + 2 (eq. 6) 00 01 10 11 /2 / (q+2) pm[1:0] /2 to outputs vco p post-divider diagram
8 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator note that the actual 10-bit post-divider value has a 2 added to the integer value q and the outputs are routed through another div/2 block. the post-divider should never be disabled unless the output bank will never be used during normal operation. the output frequency range for lvt tl outputs are from 4.9khz to 200mhz. the output frequency range for lvpecl/lvds outputs are from 4.9khz to 500mhz. spread spectrum generation pll0 and pll1 support spread spectrum generation capability, which users have the option of turning on and off. spread spectru m profile, frequency, and spread are fully programmable (within limits). the programmable spread spectrum generation parameters are tssc[3:0], nssc[3:0] , ss_offset[5:0], sd[3:0], dith, and x2 bits. these bits are in the memory address range of 0x60 to 0x67 for pll0 and 0x68 to 0x6f for pll1. th e spread spectrum generation on pll0 & pll1 can be enabled/disabled using the tssc[3:0] bits. to enable spread spectrum, set tssc > '0' and set nssc, sd[3: 0], sd[5:0], and the a[3:0] in the total m value accordingly. and to disable, set tssc = '0'. tssc[3:0] these bits are used to determine the number of phase/frequency detector cycles per spread spectrum cycle (ssc) steps. the modu lation frequency can be calculated with the tssc bits in conjunction with the nssc bits. valid tssc integer values for the modulation frequency range from 5 to 14. nssc[3:0] these bits are used to determine the number of delta-encoded samples used for a single quadrant of the spread spectrum wavefor m. all four quadrants of the spread spectrum waveform are mirror images of each other. the modulation frequency is also calculated based off the nss c bits in conjunction with the tssc bits. valid nssc integer values range from 1 to 6. ss_offset[5:0] these bits are used to program the fractional offset with respect to the nominal m integer value. for center spread, the ss_of fset should be set to '0' so the spread spectrum waveform is about the nominal m (mnom) value. for down spread, the ss_offset > '0' so the spread spectrum wavform is about the (mideal -1 = mnom) value. the downspread percentage can be thought of in terms of center spread. for example, a downspread o f -1% can also be considered as a center spread of 0.5% but with mnom shifted down by one and offset. the ss_offset has integer values ranging from 0 to 6 3. sd[3:0] these bits are used to shape the profile of the spread spectrum waveform. these are delta-encoded samples of the waveform. th ere are twelve sets of sd samples for each pll. the nssc bits determine how many of these samples are used for the waveform. the sum of these delta- encoded samples (sigma- delta-encoded samples) determine the amount of spread and should not exceed (63 - ss_offset). the maximum spread is inversely proportional to the nominal m integer value. dith this bit is for dithering the sigma-delta-encoded samples. this will randomize the least-significant bit of the input to the s pread spectrum modulator. set the bit to '1' to enable dithering. x2 this bit will double the total value of the sigma-delta-encoded-samples which will increase the amplitude of the spread spectru m waveform by a factor of two. when x2 is '0', the amplitude remains nominal but if set to '1', the amplitude is increased by x2. the following equations govern how the spread spectrum is set: t ssc = tssc[3:0] + 2 (eq. 7) n ssc = nssc[3:0] * 2 (eq. 8) sd[3:0] k = s j+1 (unencoded) - s j (unencoded) (eq. 9) where s j is the unencoded sample out of a possible 12 and sd k is the delta-encoded sample out of a possible 12. amplitude = (2*n[11:0] + a[3:0] + 1) * spread% / 100 (eq. 10) 2 if 1 < amp < 2, then set x2 bit to '1'.
9 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator modulation frequency: f pfd = f in / d (eq. 11) f vco = f pfd * m nom (eq. 12) f ssc = f pfd / (4 * nssc * tssc) (eq. 13) spread: ? = sd 0 + sd 1 + sd 2 + ? + sd 11 the number of samples used depends on the n ssc value ? 63 - ss_offset spread% = ? * 100 (eq. 14) 64 * (2*n[11:0] + a{3:0} + 1) max spread% / 100 = 1 / m nom or 2 / m nom (x2=1) profile: waveform starts with ss_offset, ss_offset + sd j , ss_offset + sd j+1 , etc. spread spectrum using sinusoidal profile ? = 63 (ss_offset = 0)
10 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator example f in = 25mhz, f out = 100mhz, fssc = 33khz with center spread of 2%. find the necessary spread spectrum register settings. since the spread is center, the ss_offset can be set to '0'. solve for the nominal m value; keep in mind that the nominal m sh ould be chosen to maximize the vco. start with d = 1, using eq.10 and eq.11. m nom = 1200mhz / 25mhz = 48 using eq.4, we arbitrarily choose n = 22, a = 3. now that we have the nominal m value, we can determine tssc and nssc by using eq.12. nssc * tssc = 25mhz / (33khz * 4) = 190 however, using eq. 7 and eq.8, we find that the closest value is when tssc = 14 and nssc = 6. keep in mind to maximize the num ber of samples used to enhance the profile of the spread spectrum waveform. tssc = 14 + 2 = 16 nssc = 6 * 2 = 12 nssc * tssc = 192 use eq.14 to determine the value of the sigma-delta-encoded samples. 2% = ? * 100 64 * 48 ? = 61.44 either round up or down to the nearest integer value. therefore, we end up with 61 or 62 for sigma-delta-encoded samples. sin ce the sigma-delta-encoded samples must not exceed 63 with ss_offset set to '0', 61 or 62 is well within the limits. it is the discretion of the user to define the shape of the profile that is better suited for the intended application. using eq.14 again, the actual spread for the sigma-delta-encoded samples of 61 and 62 are 1.99% and 2.02%, respectively. use eq.10 to determine if the x2 bit needs to be set; amplitude = 48 * (1.99 or 2.02) / 100 = 0.48 < 1 2 therefore, the x2 = '0 '. the dither bit is left to the discretion of the user. the example above was of a center spread using spread spectrum. for down spread, the nominal m value can be set one integer va lue lower to 43. note that the 5v9885c should not be programmed with tssc > '0', ss_offset = '0', and sd = '0' in order to prevent an unstable s tate in the modulator. the pll loop bandwidth must be at least 10x the modulation frequency along with higher damping (larger uz) to prevent the spread spectrum from being filtered and reduce extraneous noise. refer to the loop filter section for more detail on uz. the a[3:0] must be used for spread spectrum, even if the total multiplier value is an even integer. fractional divider there is the option for the feedback-divider to be programmed as a fractional divider for only pll0 and pll. by setting tssc > '0' and sd bits to '0', the ss_offset bits would determine the fractional divide value. see the spread spectrum generation section for more details on the tssc, sd, and ss_offset bits. the following equation governs how the fractional divide value is set. m = 2*n[11:0] + a[3:0] + 1 + ss_offset[5:0] *1/64
11 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator the spread spectrum parameters such as the modulation frequency and profile will not be enabled nor will it have any impact on the pll output when the pll is programmed for fractional divide. the following is an example of how to set the fractional divider. example f in = 20mhz, f out 1 = 168.75mhz, f out 2 = 350mhz solving for 350mhz using eq.2 and eq.3 with pll0 and spread spectrum off, 350mhz = 20mhz * (m / d)/ (p * 2) for better jitter performance, keep d as small as possible (350mhz * 2/20mhz)= (m/p) = 35 therefore, we have d = 1, m = 35 (n = 16, a = 2) for pll0 with p = 1 on output bank4 resulting in 350mhz. solving for 168.75mhz with pll1 and fractional divide enabled: 168.75mhz = 20mhz * (m / d)/(p * 2) 168.75mhz * 2/20mhz = m/p = 16.875/1 or 33.75/2 the 33.75 value is chosen to achieve the highest vco frequency possible. next step is to figure out the setting for the fracti onal divide using eq.3. 33.75 = 2*n + a + 1 + ss_offset * 1/64 integer value 33 can be determined by n and a, thus leaving 0.75 left to be solved. 2*n + a + 1 = 33 ss_offset = 64 * 0.75 = 48 therefore, we have d=1, m=33.75 (n=15, a=2, ss_offset=48) for pll1 with p=2 on an output bank resulting in 168.75mhz. the fractional divider can be determined if it is needed by following the steps in the previous example. note that the 5v9885c should not be programmed with tssc > '0', ss_offset = '0', and sd = '0' in order to prevent an unstable state in the modulator. the a[3:0] must be used and set to be greater than '2' for a more accurate fractional divide.
12 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator loop filter the loop filter for each pll can be programmed to optimize the jitter performance. the low-pass frequency response of the pll is the mechanism that dictates the jitter transfer characteristics. the loop bandwidth can be extracted from the jitter transfer. a narrow loop bandwidth is good for jitter attenuation while a wide loop bandwidth is best for low jitter generation. the specific loop filter components that can be programmed are the resistor via the rz[3:0] bits, pole capacitor via the cz[3:0] bits, zero capacitor via the cp[3:0] bits, and the charge pump current via the ip[2:0] bits. the following equations govern how the loop filter is set. resistor (rz) = 0.3k ? + rz[3:0] * 1k ? (eq. 15) zero capacitor (cz) = 6pf + cz[3:0] * 27.2pf (eq. 16) pole capacitor (cp) = 1.3pf + cp[3:0] * 0.75pf (eq. 17) charge pump current (ip) = 5 * 2 ip[2:0] a (eq. 18) parameter bits step min max units rz 4 1 0.3 15.3 k ? cz 4 27.2 6 414 pf c p 4 0.75 1.3 12.55 pf ip 3 2 n 5 640 a from pfd v dd up ip down ip rz cz cp to vco charge pump and loop filter configuration pll loop filter design is beyond the scope of this datasheet. refer to design procedures for 3-order charge-pump based plls. for the sake of simplicity, the fastest and easiest way to calculate the pll loop bandwidth (fc) given the programmable loop filter parameters is as follow s. pll loop bandwidth: charge pump gain (k ) = ip / 2 (eq. 19) vco gain (k vco ) = 950mhz/v * 2 (eq. 20) m = total multiplier value (see the pre-scalers, feedback-dividers, post-dividers section for more detail) c = rz * k * k vco * cz (eq. 21) m * (cz + cp) fc = c / 2 (eq. 22) note, the phase/frequency detector frequency (f pfd ) is typically seven times the pll closed-loop bandwidth (fc) but too high of a ratio will reduce your phase margin thus compromising loop stability.
13 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator to determine if the loop is stable, the phase margin ( m) would need to be calculated as follows. phase margin: z = 1 / (rz * cz) (eq. 23) p = cz + cp (eq. 24) rz * cz * cp m = (360 / 2 ) * [tan -1 ( c/ z) - tan -1 ( c/ p)] (eq. 25) to ensure stability in the loop, the phase margin is recommended to be > 60 but too high will result in the lock time being ex cessively long. certain loop filter parameters would need to be compromised to not only meet a required loop bandwidth but to also maintain loop stability. example fc = 150khz is the desired loop bandwidth. the total m value is 850. the ratio of p/ c should be at least 4. a rule of thumb that will help to aid the way, the p / c ratio should be at least 4. given fc and m, an optimal loop filter setting needs to be solved for that will meet both the pl l loop bandwidth and maintain loop stability. the charge pump gain should be relatively small as possible to achieve a low loop bandwidth. ip = 40ua . k * k vco = 950mhz/v * 40ua = 38000a/vs loop bandwidths c = 2 * fc = 9.42x10 5 s -1 uz = p / c = 4 (eq. 26) c 2 = p * z (eq. 27) p = cz + cp = z (1 + cz / cp) rz * cz * cp solving for cz, cp, and rz knowing c = rz * k * k vco * cz and substituting in the equations from above, m * (cz + cp) cz >>> cp, therefore, we can easily derive cp to be cp = k * k vco = 12.60pf m * c 2 * uz similarly for cz and rz cz = k * k vco * ( uz 2 - 1) = cp * ( uz 2 - 1) = 189pf m * c 2 * uz rz = m * c * uz 2 = 22.48k ? k * k vco * ( uz 2 - 1) based on the loop filter parameter equations from above, since there are no possible values of 12.60pf for cp, 189pf for cz, an d 22.48k ? for rz, the next possible values within the loop filter settings are 12.55pf (cp[3:0]=1111), 196.4pf (cz[3:0]=0111), and 15.3k ? (rz[3:0]=1111), respectively. this loop filter setting will yield a loop bandwidth of about 102khz. the phase margin must be checked for loop stability. m = (360 / 2 ) * [tan -1 (6.41x10 5 s -1 / 3.33x10 5 s -1 ) - tan -1 (6.41x10 5 s -1 / 5.54x10 6 s -1 )] = 56 although slightly below 60, the phase margin would be acceptable with a fairly stable loop.
14 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator gin2 pin gin1 pin gin0 pin pll0 configuration selection (mode 1) 0 0 0 configuration 0 0 0 1 configuration 1 0 1 0 configuration 2 0 1 1 configuration 3 1 0 0 configuration 4 1 0 1 configuration 5 1 1 0 configuration 6 1 1 1 configuration 7 configuring the multi-purpose i/os the 5v9885c can operate in four distinct modes. these modes are controlled by the mfc bit (0x04) and the i 2 c/jtag pin. the general purpose i/o pins (gin0, gin1, gin2, gin3, gin4, gin5) have different uses depending on the mode of operation. the four available modes of operat ion are: 1) manual frequency control (mfc) mode for pll0 only 2) manual frequency control (mfc) mode for all three plls 3) i 2 c programming mode 4) jtag programming mode along with the ginx pins are also goutx output pins that can take up a different function depending on the mode of operation. see table below for description. each pll's programming registers can store up to four different dx and mx configurations in combination with two different p c onfigurations in mfc modes. the post-divider should never be disabled in any of the two p configurations unless the output bank will never be used during normal operation. the pll's loop filter settings also has four different configurations to store and select from. this will be explained in the mode1 and mode2 sections. the use of the ginx pins in mfc mode control the selection of these configurations. mode1 - manual frequency control (mfc=1) mode for pll0 only in this mode, only 8 configurations of pll0 can be changed during operation. the gin0, gin1 and gin2 pins control the selection of eight different configurations (d, m, rz, cz, cp and ip) of pll0. gin3 becomes pll suspend pin, gin4 is not available to users, and gin5 become s clk_sel pin. the output gout0 will become an indicator for loss of pll lock (loss_lock). gout1 pin will become an indicator for loss of the primary clock (loss_clkin). the pll0 has 4 sets of dedicated registers for d, m, rz, cz, cp, ip and odiv. for additional 4 sets of registers, the pll0 use s registers from config2 and config3 of pll1 and pll2. the pll1 and pll2 will still be fully operational, but have only one fixed configuration in this mode, and the default configuration will be set to config0 of pll1 and config0 of pll2. (please see page 18 for register location.) the output banks will each have two p configurations that can be associated with each of the pll configurations. each of the tw o p configurations has its own set of pm bits (see the pre-scalers, feedback-dividers, post-dividers section for more detail on the pm bits). use the odiv bit to choose which post-divider configuration to associate with a specific pll configuration. to enter this mode, users must set mfc bit to ?1?, and i2c/jtag pin must be left floating. note: 1. please see detail description in loss of lock and input clock section. multi-purpose pins other signal functions signal description gin0 sdat / tdi i 2 c serial data input / jtag serial data input gin1 sclk / tck i 2 c clock input / jtag clock input gin2 tms jtag control signal to the tap controller state machine gin3 suspend suspends all outputs of pll (active high) gin4 trst jtag active low input to asynchronously reset the bst gin5 clk_sel reference clock select between xtalin/refin and clkin gout0 tdo / loss_lock jtag serial data output / detects loss of pll lock (1) gout1 loss_clkin detects loss of the primary clock source (1)
15 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator mode3 - i 2 c programming mode in this mode, gin0, gin1, gin3 and gin5 become sdat (i 2 c data), sclk (i 2 c clock), suspend and clk_sel signal pins, respectively. the output gout0 will become an indicator for loss of pll lock (loss_lock). gout1 pin will become an indicator for loss of the primary clock (l oss_clkin). gin2 and gin4 are not available to users. to enter this mode, i 2 c/jtag pin must be set high. mode4 - jtag programming mode in this mode, gin0, gin1, gin2, gin3, gin4 and gin5 will become tdi (jtag data in), tck (jtag clock), tms (jtag control signal) , suspend, trst (jtag reset) and clk_sel signal pins, respectively. the output gout0 will become jtag tdo signal, and gout1 will be an indicato r for loss of the selected clock (loss_clkin). to enter this mode, i 2 c/jtag pin must be set low. mode2 - manual frequency control (mfc=0) mode for all plls in this mode, the configuration of pll0, pll1, and pll2 can be changed during operation. the ginx pins are used to control the selection of up to four different dx, mx, rzx, czx, cpx, and ipx configurations for each pll. gin0 and gin1 become configuration selection pins for d0 and m0 of pll0, gin2 and gin3 become configuration selection pins for pll1, and gin4 and gin5 become configuration selection pins for d2 and m2 of pll2. the output gout0 will become an indicator for loss of pll lock (loss_lock). gout1 pin will become an indicator for loss of the primary clock (loss_clkin). the output banks will have two different p configurations to choose from for each of the four pll configurations. each of the two p configurations has its own set of pm bits (see the pre-scalers, feedback-dividers, post-dividers section for more detail on the pm bits). use the odiv bit to choose which post-divider configuration to associate with a specific pll configuration. for example, if odiv2_config2=1, then when config2 is selected qx[9:0]_config1 is selected as the post-divider value to be used. note that there is an odivx bit for each of the pll configurations. in this way, the post-divider values can change with the configuration. to enter this mode, users must set mfc bit to "0", and i 2 c/jtag pin must be left floating. gin1 pin gin0 pin pll0 configuration selection (mode 2) 0 0 configuration 0 0 1 configuration 1 1 0 configuration 2 1 1 configuration 3 gin3 pin gin2 pin pll1 configuration selection (mode 2) 0 0 configuration 0 0 1 configuration 1 1 0 configuration 2 1 1 configuration 3 gin5 pin gin4 pin pll2 configuration selection (mode 2) 0 0 configuration 0 0 1 configuration 1 1 0 configuration 2 1 1 configuration 3 manual frequency control modes multi-purpose pins mode1 mode2 jtag i 2 c gin0 gin0 gin0 tdi sdat gin1 gin1 gin1 tck sclk gin2 gin2 gin2 tms n/a gin3 suspend gin3 suspend suspend gin4 n/a gin4 trst n/a gin5 clk_sel gin5 (1) clk_sel clk_sel gout0 loss_lock loss_lock tdo loss_lock gout1 loss_clkin loss_clkin loss_clkin loss_clkin note: 1. the pll(s) will lock onto the primary clock and the manual switchover can be controlled by the primclk bit.
16 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator understanding the gin signals during power up, the part will virtually be in mfc mode2, therefore, the values of gin4, gin3, gin2, gin1 and gin0 will be latc hed and used for pll configuration selection, regardless of the state of the i 2 c/jtag pin. gin5 is not latched, and will assume the low state internally when in programming mode. this means that when in programming mode, the pll configuration can only be changed by writing directly to the registers of the currently selected configuration. when in mfc mode 2, configuration 0 or 1 (gin5=0) should be selected if you do not want to change configurations when entering or leaving programming mode. the gin pins should be held low during power up to select configuration0 as default. when not in programming mode, the gin inputs directly control the selected configuration. the internal ginx signals can be ind ividually disabled via programming the ginen bits (0x06). when disabled by setting ginenx to "0", the ginx inputs may be left floating, but during po wer up, the gin pins will still latch. disabled inputs are interpreted as low by the internal state machines. even if disabled, gin2, gin1, gin0 and gin4 pins will be enabled if required for i 2 c or jtag programming functions when in programming mode. the suspend and clk_sel functions on the gin3 and gin5 pins, respect ively, will be rendered completely non-functional when disabled. shutdown/suspend/enable of outputs there are two external pins along with internal bits that control the enabling/disabling of the output banks. the two pins ar e the shutdown/oe pin and the gin3/suspend pin. the shutdown/oe pin can be programmed to function as an output enable or global shutdown. the polarity of the shutdown/ oe signal pin can be programmed to be either active high or low with the sp bit (0x1c). when sp is "0", the pin becomes activ e high and when sp is "1", the pin becomes active low. the sh bit(0x1c) determines the function of the shutdown/oe signal pin. if sh is "1", the s ignal pin is shutdown and functions as a global shutdown. this will override the oex (0x1c), osx (0x1d), and pllsx (0x1e) bits. if sh is "0", the signal pin is oe and functions as an enable/disable of the output banks. if used as an output enable/disable, each output bank can be individually programmed to be enabled or disabled by the oe pin.by setting oex bits to "1". if the oe signal pin is asserted, the output banks that has their corresponding oex bit set to "1" will be disabled. the oemx bits determine the outputs' disable state. when set to "0x" the outputs will be tristated. when set to "10", the outputs will be pulled low. when set to "11", the outputs will be pulled high. inverted outputs will be parked in the opposite state. if the oex bits are set to "0", the s tates of the corresponding output banks will not be impacted by the state of the oe pin. to individually enable/disable via programming instead of the oe pin, hard wi re the oe pin to vdd or gnd (depending if it is active high or low) as if to disable the outputs. then toggle the oex bits to either "0" to enable or "1" to disable. when the chip is in shutdown, the outputs, the reference oscillator, and the i 2 c /jtag pin are powered down. the outputs will be tristated and the i 2 c /jtag pin will be set to mfc mode (mid level). programming will not be allowed. the ginx pins and clock inputs remain operati onal. the pll is not disabled. the shutdown pin must be reasserted in order to program the part or to resume operation. the gin3/suspend pin, when used as a suspend function, can be used to power down the pll and/or output banks.. each output bank can be individually programmed to be enabled or disabled by the suspend signal pin by setting the osx bits to "1". if the suspend si gnal pin is asserted, the output banks that has their corresponding osx bit set to "1" will be powered down and outputs tristated. if the osx bits are set to " 0", the states of the corresponding output banks will not be impacted by the state of the suspend pin. there is also an option to suspend individual plls by sett ing the pllsx bits (0x1e) to "1". this will associate the pll to the suspend pin. when the pin is asserted, the corresponding plls will be powered down. it will not only power down the pll but also any output bank associated with it. the pllsx bits will override the osx bits. in the event of a pll suspend, the pll must achieve lock again after it has been re-enabled, in the event of a global shutdow n, the pll does not have to re-acquire lock since it is not disabled.
17 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator mfc = 0 manual frequency control (mfc) block diagram notes: this illustration shows how the configurations are arranged for each pll. there is an odiv bit associated with each of the fou r configurations. - gin0 and gin1 control four configurations from pll0. - gin2 and gin3 control four configurations from pll1. - gin4 and gin4 control four configurations from pll2. - odiv from each configuration determines the selection of two output divider px configurations. config0 config1 output divider p2 odiv config0 config1 config2 config3 pll0 prescaler "d" config0 config1 config2 config3 odiv odiv odiv odiv vco multiplier "m" config0 config1 output divider p3 odiv config0 config1 config2 config3 pll1 prescaler "d" config0 config1 config2 config3 pll2 prescaler "d" config0 config1 config2 config3 odiv odiv odiv odiv vco multiplier "m" output mux config0 config1 config2 config3 odiv odiv odiv odiv vco multiplier "m"
18 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator mfc = 1 notes: this illustration shows how the configurations are arranged for pll0. register location for config_4 and config_5 are taken fr om pll1, and config_6 and config_7 are taken from pll2. there is an odiv bit associated with each of the configurations. - gin0, gin1, and gin2 control eight shaded configurations for pll0. - odiv from each configuration determines the selection of two output divider px configurations. manual frequency control (mfc) block diagram config0 config1 output divider p2 odiv config0 config1 config2 config3 pll0 prescaler "d" config0 config1 config2 config3 odiv odiv odiv odiv vco multiplier "m" config0 config1 output divider p3 odiv config0 config4 config5 pll1 prescaler "d" config0 config4 config5 odiv odiv odiv vco multiplier "m" config0 config6 config7 pll2 prescaler "d" config0 config6 config7 odiv odiv odiv vco multiplier "m" output mux
19 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator block diagram for shutdown/oe control signal note: this illustration shows the internal logic behind the shutdown/oe pin and the bits associated with it. oe2 01 10 11 q2 + 2 /2 pm2 /2 01 10 11 q3 + 2 /2 pm3 /2 oe3 01 10 11 q6 + 2 /2 pm6 /2 oe6 01 10 11 q5 + 2 /2 pm5 /2 oe5 01 10 11 q4 + 2 /2 pm4 /2 oe4 oe1 mux out1 out3 out2 out6 out4 out4 out5 out5 shutdown/oe sp sh oe mode global shutdown mode: assert to shutdown power on the outputs and 3-level pin
20 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator power up and power saving features if a global shutdown is enabled, shutdown pin asserted, most of the chip except for the plls will be powered down. in order to have a complete power down of the chip, the plls must be powered down via the suspend function or by setting the pre-scaler bits to '0x00' and disable the internal ginx signals via the enable bits at memory address 0x05. note that the register bits will not lose their state in the event of a chip power-down. the only possibility that the register bits will lose their state is if the part was power-cycled. after coming out of shutdown mode, the plls will require time to relock. during power up, the values of gin4, gin3, gin2, gin1 and gin0 will be latched and used for pll configuration selection, regard less of the state of the i 2 c/jtag pin and ginx being disabled via the ginenx bits. gin5 will have an internal state of low. the gin pins should be held low during power up to select configuration0 as default. the output levels will be at an undefined state during power up. the post-divider should never be disabled via pm bits after power up, or else it will render the output bank completely non-f unctional during normal operation, (unless the output bank itself will not be used at all). during power up, the v dd ramp must be monotonic. loss of lock and input clock the device employs a loss of lock and loss of input clock detection circuitry. the gout0/loss_lock and gout1/loss_clkin are th e outputs that indicate such failures. loss_lock signal will be asserted if any of the three powered up plls loses frequency lock for any e vent other than pll shutdown. lock is determined by checking that the reference and feedback clocks are within 1/2 period of each other.loss_lock signal may be falsely asserted when - spread spectrum is turned on for any of the plls - fractional divider is used for any of the plls - the reference and feedback clocks are not within 1/2 period of each other. loss_clkin is asserted when the currently selected clock is lost or is asserted when both clocks are lost. in the event of the selected clock being absent up on power up, the loss of the selected clock detection circuitry will reference an internal oscillator. loss_lock and loss_clkin cannot be used as reliable inputs to other devices. switchover modes the idt5v9885c features redundant clock inputs which supports both automatic and manual switchover mode. these two modes are d etermined by the configuration bits, sm (0x34). the primary clock source can be programmed, via the primclk bit, to be either xtalin/refin or clkin, which is determined by the primclk bit. the other clock source input will be considered as the secondary source. this is more detailed in the 'reference clock input pins and selection'. note that the switchover modes are asynchronous. if the reference clocks are directly routed to outx with no phase relationship, short pulses can be generated during switchover. the automatic switchover mode will work only when the pri mary clock source is xtalin/refin. manual switchover mode when sm[1:0] is "0x", the redundant inputs are in manual switchover mode. in this mode, clk_sel pin is used to switch between the primary and secondary clock sources. as previously mentioned, the primary and secondary clock source setting is determined by the primclk b it. during the switchover, no glitches will occur at the output of the device, although there may be frequency and phase drift, depending on t he exact phase and frequency relationship between the primary and secondary clocks. if gout1 is used as loss_clkin, it indicates loss of primary c lock. automatic switchover mode when sm[1:0] is "11", the redundant inputs are in automatic revertive switchover mode.
21 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator programming interface block eeprom cell plls and control blocks i c or jtag interface 2 write enable i/os i/os volatile configuration non-volatile configuration note: diagram does not represent actual number of die on chip. high level block diagram for configuration scheme revertive the input clock selection will switch to the secondary clock source when there are no transitions on the primary clock source. loss_clkin signals will be asserted. after a stable and valid primary clock source is present, the input clock selection will automatically switch bac k to the primary clock source and loss_clkin signal will be deasserted. the clk_sel pin can be left floating in this auto-revertive mode. note that both clock in puts must be at the same frequency (within1000 ppm) in order for the auto-revertive switchover to function properly. if both reference clocks are at di fferent frequencies, the device will always remain on the primary clock unless it is absent for two secondary clock cycles. clock switch matrix and outputs all three pll outputs and the currently selected input clock source are routed into and through a clock matrix. the user is abl e to select which pll output and clock source is routed to which output bank via the srcx bits (0x34, 0x35). each output bank has its own set of src bits. refer to the ram table for more information. note that out1 will be based off the reference clock and the only output bank toggling under the default ra m bit settings. outputs 1, 2 and 3 are 3.3v lvttl. outputs banks 4 and 5 can be 3.3v lvttl, lvpecl or lvds. the lvds and lvpecl selection is determined by the lvlx bits (0x54, 0x58). each output bank has individual slew-rate control (slewx bits). each output can be individuall y inverted (invx bits); when using lvpecl or lvds modes, one of the outputs in each lvpecl/lvds pair should be inverted. all output banks except out1 have a programmable 10-bit post-divider (qx bits) with two selectable divide configurations via the odivx bits. there are four settings for the programmable slew rate, 0.7v/ns, 1.25v/ns, 2v/ns, and 2.75v/ns; this only applies to the 3.3v l vttl outputs. the differential outputs are not slew rate programmable in lvpecl or lvds modes. slew4 and/or slew5 must be set to 2.75v/ns for s table output operation . for lvttl output frequency rates higher than 100mhz, a slew rate of 2v/ns or greater should be selected. the post-dividers can be disabled using the pmx bit, which is described in the pre-scaler, feedback-divider, and post-divider section. each output can also be enabled /disabled, which is described in the 'shutdown/suspend/enable of outputs' section. refer to the ram table for all binary settings.
22 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator programming the device i 2 c and jtag may be used to program the 5v9885c. the i 2 c/jtag pin selects the i 2 c when high and jtag when low. note that the trst pin needs to be low for i 2 c mode. hardwired parameters for the idt5v9885c jtag identification number = 32'b0000_0000001110101100_00000110011_1 device (slave) address = 7'b1101010 id byte for the 5v9885c = 8'b00010000 i 2 c programming the 5v9885c is programmed through an i 2 c-bus serial interface, and is an i 2 c slave device. the read and write transfer formats are supported. the first byte of data after a write frame to the correct slave address is interpreted as the register address; this address auto-increme nts after each byte written or read. the frame formats are shown below. sda scl s start condition data frame data is stable during clock high stop condition p scl sda msb lsb r/w 7-bit slave address r/w 0 - slave will be written by master 1 - slave will be read by master the first byte transmitted by the master is the slave address followed by the r/w bit. the slave acknowledges by sending a "1" bit. ack from slave 1101010 figure 1: framing figure 2: first byte transmittetd on i 2 c bus each frame starts with a "start condition" and ends with an "end condition". these are both generated by the master device.
23 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator external i 2 c interface condition progwrite writes can continue as long as a stop condition is not sent and each byte will increment the register address. progread s address r/w ack command code register data p ack ack ack 7-bits 0 1-bit 8-bits: xxxxxx00 1-bit 8-bits 1-bit 8-bits 1-bit s address r/w ack command code register p ack ack 7-bits 0 1-bit 8-bits: xxxxxx00 1-bit 8-bits 1-bit ack 8-bits data_1 1-bit sr address r/w ack id byte nack 7-bits 1 1-bit 8 bits 1-bit p ack 8-bits data_2 1-bit ack 8-bits data_last 1-bit figure 3: progwrite command frame note: if the expected read command is not from the next higher register to the previous read or write command, then set a known "read" register address prior to a read operation by issuing the following command: key: from master to slave from master to slave, but can be omitted if followed by the correct sequence normally data transfer is terminated by a stop condition generated by the master. however, if the master still wishes to commu nicate on the bus, it can generate a repeated start condition, and address another slave address without first generating a stop condition. from slave to master symbols: ack - acknowledge (sda low) nack - not acknowledge (sda high) sr - repeated start condition s - start condition p - stop condition 1234 1 23 4 1234 the user can ignore the stop condition above and use a repeated start condition instead, straight after the slave acknowledgeme nt bit (i.e., followed by the progread command): note: figure 4b above by itself is the progread command format. the id byte for the 5v9885c is 10hex. each byte recieved incr ements the register address. figure 4a: prior to progread command set register address figure 4b: progread command frame
24 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator eeprom interface the idt5v9885c can also store its configuration in an internal eeprom. the contents of the device's internal programming regis ters can be saved to the eeprom by issuing a save instruction (progsave) and can be loaded back to the internal programming registers by issuing a resto re instruction (progrestore). to initiate a save or restore using i 2 c, only two bytes are transferred. the device address is issued with the read/write bit set to "0", followed by the appropriate command code. the save or restore instruction executes after the stop condition is issued by the master, during which time the idt5v9885c will not generate acknowledge bits. the idt5v9885c will acknowledge the instructions after it has completed execution of them. during that time , the i 2 c bus should be interpreted as busy by all other users of the bus. using jtag, the progsave and progrestore instructions selects the bypass register path for shifting the data from tdi to tdo du ring the data register scanning. during the execution of a progsave or progrestore instruction, the idt5v9885c will not accept a new programming instruction (re ad, write, save, or restore). all non-programming jtag instructions will function properly, but the user should wait until the save or restore is complete be fore issuing a new programming instruction. if a new programming instruction is issued before the save or restore completes, the new instruction is ignored, and the bypass register path remains in effect for shifting data from tdi to tdo during data register scanning. the time it takes for the save (t save ) and restore (t restore ) instructions to complete is: t save = 100ms max, t restore = 10 ms max progsave progrestore note: progwrite is for writing to the 5v9885c registers. progread is for reading the 5v9885c registers. progsave is for saving all the contents of the 5v9885c registers to the eeprom. progrestore is for loading the entire eeprom contents to the 5v9885c registers. s address r/w ack command code ack 7-bits 0 1-bit 8-bits:xxxxxx01 1-bit p s address r/w ack command code ack 7-bits 0 1-bit 8-bits:xxxxxx10 1-bit p jtag interface in addition to the ieee 1149.1 instructions extest, sample/preload, clamp, high-z and bypass, the 5v9885c allows access to internal programming registers using the regaddr (set register address), regdatar (read register) and regdatw (write register instructions. data is always accessed by byte, and the register address increments after each read or write. the full instruction set follows. the idt5v9885c will be updating the registers during programming. the jtag tap controller can be reset in one of four ways: 1) power up in jtag mode 2) power up in i 2 c mode and then go into jtag mode, or go out of and back into jtag mode with the i 2 c/jtag pin 3) apply trst while in jtag mode 4) apply five rising edges of tck with tms high while in jtag mode ir (3) ir (2) ir (1) ir (0) instructions 0 0 0 0 extest (1) 0 0 0 1 sample/preload (1) 0 0 1 0 idcode (1) 0 0 1 1 regaddr (2) 0 1 0 0 regdataw / progwrite (3) 0 1 0 1 regdatar / progread (4) 0 1 1 0 progsave (5) 0 1 1 1 progrestore (6) 1 0 0 0 clamp (1) 1 0 0 1 highz (1,7) 1 1 1 1 bypass (1) jtag instruction register description notes: 1. ieee 1149.1 definition 2. regaddr is for setting a specific 5v9885c register address. 3. regdataw/progwrite is for writing to the 5v9885c registers. 4. regdatar/progread is for reading the 5v9885c registers. 5. progsave is for saving all the contents of the 5v9885c registers to the eeprom. 6. progrestore is for loading the entire eeprom contents to the 5v9885c registers. 7. the oems bits for out1-6 must be set for tri-state when using the highz instruction
25 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator standard jtag timing note: t1 = t tclklow t2 = t tclkhigh t3 = t tclkfall t4 = t tclkrise t5 = t rst (reset pulse width) t6 = t rsr (reset recovery) tclk tdi/tms tdo trst t tclk t1 t2 t3 t4 t5 t6 t ds t dh t do tdo jtag ac electrical characteristics note: 1. guaranteed by design. system interface parameters symbol parameter min. max. units t do data output (1) ?20 ns t doh data output hold (1) 0 ? ns t ds data input, t rise = 3ns 10 ? ns t dh data input, t fall = 3ns 10 ? ns note: 1. 50pf loading on external output signals. symbol parameter min. max. units t tclk jtag clock input period 100 ? ns t tclkhigh jtag clock high 40 ? ns t tclklow jtag clock low 40 ? ns t tclkrise jtag clock rise time ? 5 (1) ns t tclkfall jtag clock fall time ? 5 (1) ns t rst jtag reset 50 ? ns t rsr jtag reset recovery 50 ? ns in order for the save and restore instructions to function properly, the idt5v9885c must not be in shutdown mode (shutdown pin asserted). in the event of an interrupt of some sort such as a power down of the part in the middle of a save or restore operation, the contents to or from the eeprom will be partially loaded, and a crc error will be generated. the cerr bit (0x81) will be asserted to indicate that an error has occurred. the l oss_lock signal will also be asserted. on power-up of the idt5v9885c, an automatic restore is performed to load the eeprom contents into the internal programming regi sters. the auto-restore will not function properly if the device is in shutdown mode (shutdown pin asserted). the idt5v9885c will be ready to accept a programming instruction once it acknowledges its 7-bit i 2 c address.
26 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator i 2 c bus dc characteristics symbol parameter conditions min typ max unit v ih input high level 0.7 * v dd v v il input low level 0.3 * v dd v v hys hysteresis of inputs 0.05 * v dd v i in input leakage current 1.0 a v ol output low voltage i ol = 3 ma 0.4 v i 2 c bus ac characteristics for standard mode symbol parameter min typ max unit f sclk serial clock frequency (sclk) 0 100 khz t buf bus free time between stop and start 4.7 s t su : start setup time, start 4.7 s t hd : start hold time, start 4 s t su : data setup time, data input (sdat) 250 ns t hd : data hold time, data input (sdat) (1) 0 s t ovd output data valid from clock 3.45 s c b capacitive load for each bus line 400 pf t r rise time, data and clock (sdat, sclk) 1000 ns t f fall time, data and clock (sdat, sclk) 300 ns t high high time, clock (sclk) 4 s t low low time, clock (sclk) 4.7 s t su : stop setup time, stop 4 s i 2 c bus ac characteristics for fast mode symbol parameter min typ max unit f sclk serial clock frequency (sclk) 0 400 khz t buf bus free time between stop and start 1.3 s t su : start setup time, start 0.6 s t hd : start hold time, start 0.6 s t su : data setup time, data input (sdat) 100 ns t hd : data hold time, data input (sdat) (1) 0 s t ovd output data valid from clock 0.9 s c b capacitive load for each bus line 400 pf t r rise time, data and clock (sdat, sclk) 20 + 0.1 * c b 300 ns t f fall time, data and clock (sdat, sclk) 20 + 0.1 * c b 300 ns t high high time, clock (sclk) 0.6 s t low low time, clock (sclk) 1.3 s t su : stop setup time, stop 0.6 s note: 1. a device must internally provide a hold time of at least 300ns for the sdat signal (referred to the v ihmin of the sclk signal) to bridge the undefined region of the falling edge of sclk. note: 1. a device must internally provide a hold time of at least 300ns for the sdat signal (referred to the v ihmin of the sclk signal) to bridge the undefined region of the falling edge of sclk.
27 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator symbol description max unit v dd internal power supply voltage -0.5 to +4.6 v v i input voltage -0.5 to +4.6 v v o output voltage (2) -0.5 to v dd + 0.5 v t j junction temperature 150 c t stg storage temperature ?65 to +150 c absolute maximum ratings (1) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. not to exceed 4.6v. note: 1. capacitance levels characterized but not tested. symbol parameter min. typ. max. unit c in input capacitance ? 4 ? pf crystal specifications xtal_freq crystal frequency 8 ? 50 mhz xtal_min minimum crystal load capacitance ? 3.5 ? pf xtal_max maximum crystal load capacitance ? 35.4 ? pf crystal load capacitance resolution ? 0.125 ? xtal_v pp voltage swing (peak-to-peak, nominal) ? 2.3 ? v capacitance (t a = +25c, f = 1mhz, v in = 0v) (1) symbol description min. typ. max. unit v dd power supply voltage for lvttl 3 3.3 3.6 v power supply voltage for lvds/lvpecl 3.135 3.3 3.465 t a operating temperature, ambient ?40 ? +85 c c load_out maximum load capacitance (lvttl only) ? ? 15 pf f in external reference crystal 8 ? 50 mhz external reference clock, industrial 1 ? 400 t pu power-up time for all v dd s to reach minimum specified voltage 0.05 ? 5 ms (power ramps must be monotonic) recommended operating conditions
28 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator power supply characteristics for lvttl outputs symbol parameter test conditions typ. max unit i ddq quiescent v dd power supply current ref = low 6 12 ma outputs enabled, all outputs unloaded i ddd dynamic v dd power supply v dd = max., c l = 0pf 40 60 a/mhz current per output f reference clock = 33mhz, c l = 15pf 26 40 i tot total power v dd supply current f reference clock = 133mhz, c l = 15pf 80 120 ma f reference clock = 200mhz, c l = 15pf 112 170 notes: 1. these inputs are normally wired to v dd , gnd, or left floating. if these inputs are switched dynamically after powerup, the function and timing of the outputs may be glitched, and the pll may require additional t aq time before all datasheet limits are achieved. 2. dividers must reload reprogrammed values via power-on reset or terminal count reload in order to ensure low-power mode. dc electrical characteristics over operating range symbol parameter test conditions min. typ. max. unit v ihh input high voltage level (1) i 2 c/jtag 3-level input v dd ? 0.4 ? ? v v imm input mid voltage level (1) i 2 c/jtag 3-level input v dd /2 ? 0.2 ? v dd /2 + 0.2 v v ill input low voltage level (1) i 2 c/jtag 3-level input ? ? 0.4 v v in = v dd high level ? ? 200 i 3 3-level input dc current v in = v dd /2 mid level ?50 ? +50 a v in = gnd low level ?200 ? ? i dd total power supply current 2 outputs @166mhz; 4 outputs @ 83mhz ? 120 ? ma (3.3v supply, v dd ) 2 outputs @20mhz; 4 outputs @ 40mhz ? 40 ? i dds total power supply current in global shutdown mode ? 2 ? ma shutdown mode (2) (plls, dividers, outputs, etc. powered down) dc electrical characteristics for 3.3v lvttl (1) symbol parameter test conditions min. typ. max. unit i oh output high current v oh = v dd - 0.5, v dd = 3.3v 0.3v 12 24 ? ma i ol output low current v ol = 0.5v, v dd = 3.3v 0.3v 12 24 ? ma v ih input voltage high 2 ? ? v v il input voltage low ? ? 0.8 v i ih input high current (2 )v in = v dd ?? 10 a i il input low current v in = 0v ? ? 10 a i ozd output leakage current 3-state outputs ? ? 10 a notes: 1. see recommended operating range table. 2. i ih specification does not apply to inputs with internal pull-down.
29 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator dc electrical characteristics for lvds symbol parameter min. typ. max unit v ot (+) differential output voltage for the true binary state 247 ? 454 mv v ot (-) differential output voltage for the false binary state -247 ? -454 mv ? v ot change in v ot between complimentary output states ? ? 50 mv v os output common mode voltage (offset voltage) 1.125 1.2 1.375 v ? v os change in v os between complimentary output states ? ? 50 mv i os outputs short circuit current, v out + or v out - = 0v or v dd ?924ma i osd differential outputs short circuit current, v out + = v out -?612ma power supply characteristics for lvds outputs (1) symbol parameter test conditions (2) typ. max unit i ddq quiescent v dd power supply current ref = low 68 90 ma outputs enabled, all outputs unloaded i ddd dynamic v dd power supply v dd = max., c l = 0pf 30 45 a/mhz current per output f reference clock = 100mhz, c l = 5pf 86 130 i tot total power v dd supply current f reference clock = 200mhz, c l = 5pf 100 150 ma f reference clock = 400mhz, c l = 5pf 122 190 power supply characteristics for lvpecl outputs (1) symbol parameter test conditions (2) typ. max unit i ddq quiescent v dd power supply current ref = low 86 110 ma outputs enabled, all outputs unloaded i ddd dynamic v dd power supply v dd = max., c l = 0pf 35 50 a/mhz current per output f reference clock = 100mhz, c l = 5pf 120 180 i tot total power v dd supply current f reference clock = 200mhz, c l = 5pf 130 190 ma f reference clock = 400mhz, c l = 5pf 140 210 dc electrical characteristics for lvpecl symbol parameter min. typ. max unit v oh output voltage high, terminated through 50 ? tied to v dd - 2v v dd - 1.2 ? v dd - 0.9 v v ol output voltage low, terminated through 50 ? tied to v dd - 2v v dd - 1.95 ? v dd - 1.61 v v swing peak to peak output voltage swing 0.55 ? 0.93 v notes: 1. output banks 4 and 5 are toggling. other output banks are powered down. 2. the termination resistors are excluded from these measurements. notes: 1. output banks 4 and 5 are toggling. other output banks are powered down. 2. the termination resistors are excluded from these measurements.
30 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator ac timing electrical characteristics (spread spectrum generation = off) symbol parameter test conditions min. typ. max unit f in input frequency input frequency limit 1 (1) ? 400 m h z 1/t1 output frequency single ended clock output limit (lvttl) 0.0049 ? 200 m h z differential clock output limit (lvpecl/ lvds) 0.0049 ? 500 f vco vco frequency vco operating frequency range 10 ? 1200 m h z f pfd pfd frequency pfd operating frequency range 0.4 (1) ? 400 m h z f bw loop bandwidth based on loop filter resistor and capacitor values 0.03 ? 40 m h z t2 input duty cycle duty cycle for input 40 ? 60 % t3 output duty cycle measured at v dd /2, f out 200mhz 45 ? 55 % measured at v dd /2, f out > 200mhz 40 ? 60 slew rate single-ended output clock rise and fall time, ? 2.75 ? slewx(bits) = 00 20% to 80% of v dd (output load = 15pf) slew rate single-ended output clock rise and fall time, ? 2 ? t4 (2) slewx(bits) = 01 20% to 80% of v dd (output load = 15pf) v/ns slew rate single-ended output clock rise and fall time, ? 1.25 ? slewx(bits) = 10 20% to 80% of v dd (output load = 15pf) slew rate single-ended output clock rise and fall time, ? 0.75 ? slewx(bits) = 11 20% to 80% of v dd (output load = 15pf) rise times lvds, 20% to 80% ? 850 ? t5 fall times ? 850 ? ps rise times lvpecl, 20% to 80% ? 500 ? fall times ? 500 ? t6 output three-state timing time for output to enter or leave three-state mode ? ? 150 + ns after shutdown/oe switches 1/f outx t7 clock jitter (3,7) peak-to-peak period jitter, f pfd > 20mhz ? ? 150 ps clk outputs measured at v dd /2 f pfd < 20mhz ? 200 ? t8 output skew skew between output to output on the same bank ? ? 150 ps (bank 4 and bank 5 only) (4, 5) t9 lock time pll lock time from power-up (6) ?1020ms t10 lock time (8) pll lock time from shutdown mode ? 20 100 s notes: 1. practical lower input frequency is determined by loop filter settings. 2. a slew rate of 2v/ns or greater should be selected for output frequencies of 100mhz and higher. 3. input frequency is the same as the output with all output banks running at the same frequency. 4. skew measured between all in-phase outputs in the same bank. 5. skew measured between the cross points of all differential output pairs under identical input and output interfaces, transiti ons and load conditions on any one device. 6. includes loading the configuration bits from eeprom to pll registers. it does not include eeprom programming/write time. 7. guaranteed by design but not production tested. actual jitter performance may vary depending on the configuration. 8. actual pll lock time depends on the loop configuration. spread spectrum generation specifications symbol parameter description min. typ. max unit f in input frequency input frequency limit 1 (1) ? 400 m h z f mod mod freq modulation frequency ? 33 ? khz f spread spread value amount of spread value (programmable) - down spread -0.5, -1, -2.5, -3.5, -4 %f out amount of spread value (programmable) - center spread -2.0 to +2.0 note: 1. practical lower input frequency is determined by loop filter settings.
31 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator outputs v dd gnd 0.1 f c load clk out test circuits and conditions (1) test circuits for dc outputs other termination scheme (block diagram) outputs gnd c load clk out c load clk out r load v dd -2v outputs gnd outputs gnd c load clk out c load clk out r load v dd -2v c load clk out r load lvttl: -15pf for each output lvpecl: - 50 ? ? ? ? ? to v dd -2v for each output with 5pf lvds: - 100 ? ? ? ? ? between differential outputs with 5pf note: 1. all v dd pins must be tied together.
32 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator ram (programming register) tables xdrv=crystal drive strength ("00" = 1.4v, "01" = 2.3v, "10"= 3.2v pk-pk sw ing typical, "11"=xtal_in w ith external clock- def ault); when "11", xtalcap[7:0] value must also be set to "0". bits 7,6, 3, 2, 1, 0 are reserved and should be set to "0" xtal load cap = 3.5pf+ (0.125 x xtalcap[7:0]) , 3.5pf to 35.4pf; each xtal pin to gnd; (for example, "00000001"=0.125pf, "00000010"=0.25pf, "00000100"=0.5pf); def ault = "00000000"; no registers exist. mfc=manual frequency control mode ('0'=all pll control (def ault), "1"=pll0 control only ); ginen0 to ginen5=ginx pins enable bits, ("1"=enable (def ault), "0"=no connect (internal state w ill be "low ")); pll0 loop filter setting addr 76543210 register hex value 7 6543210 0x00 0x01 0x02 0x03 0x04 00000000 00 mfc 0x05 1 1 1 1 1 1 1 1 ff gi nen5 ginen4 gi ne n3 gin en2 ginen1 gin en0 0x06 00110000 30 0x07 00000000 00 0x08 00000000 00 odiv0_config0 0x09 00000000 00 odiv0_config1 0x0a 00000000 00 odiv0_config2 0x0b 00000000 00 odiv0_config3 0x0c 00000000 00 0x0d 00000000 00 0x0e 00000000 00 0x0f 00000000 00 0x10 00000000 00 0x11 00000000 00 0x12 00000000 00 0x13 00000000 00 bit # bit # d0 [7:0]_config3 d0 [7:0]_config0 rz0[3:0]_config3 ip0[2:0]_config3 cp0[3:0]_config1 cz0[3:0]_config0 cp0[3:0]_config0 cz0[3:0]_config1 cz0[3:0]_config3 cp0[3:0]_config2 d0 [7:0]_config1 cz0[3:0]_config2 cp0[3:0]_config3 d0 [7:0]_config2 rz0[3:0]_config1 reserved ip0[2:0]_config1 rz0[3:0]_config2 ip0[2:0]_config2 ip0[2:0]_config0 rz0[3:0]_config0 xdrv[1:0] xtalcap[7:0] des cr ipt ion xdrv= crystal drive strength ("00" = 1.4v, "01" = 2.3v, " 10"= 3.2v pk-pk swing typi cal, " 11"=xta l_in with external clock-default ); when " 11", xta lcap[7:0] value must also be set to "0". b its 7,6, 3, 2, 1, 0 are reserved and should be set to "0" xtal l oad cap = 3.5pf+ (0.125 x xtalcap[7:0]) , 3.5pf to 35.4pf; each xtal pin to gnd; (for example, "00000001"=0.125pf, "00000010"=0.25pf, "00000100" =0.5pf); default = "00000000" ; no registers exist mfc=manual frequency control mode ('0'=all pll control (default), "1"= pll0 control only ); ginen0 to ginen5=ginx pins enable bits, ("1"=enable (default), "0"=no connect (internal state will be "low")); p ll0 loop filter setting odiv0_configx=determines which one of the 2 "qx-divider" configurations to use wi pll0 input divider d0 setting 0x14 00000000 00 0x15 00000000 00 0x16 00000000 00 0x17 00000000 00 0x18 00000000 00 0x19 00000000 00 0x1a 00000000 00 0x1b 00000000 00 0x1c 0 0 0 0 0 0 0 0 00 sp sh oe6 oe5 oe4 oe3 oe 2 oe1 0x1d 01000000 40 okc os6 os5 os4 os3 os2 os1 0x1e 00000000 00 plls2 plls1 plls0 n0 [7:0]_config0 n0[11:8]_config0 a0[3:0]_config3 n0 [7:0]_config2 a0[3:0]_config0 a0[3:0]_config2 a0[3:0]_config1 n0[11:8]_config1 n0[11:8]_config3 n0[11:8]_config2 n0 [7:0]_config3 n0 [7:0]_config1 sp=shutdown/oe polarity for shutdown/oe signal pin, ("0"= active high (default), "1"= active low); oe x=output di sable functi on for outx, ("1"=outx disabled based on oe pin (default for out2-6, disable mode is defined by oemx bits), "0"= outputs enabled and no association with oe pin (default)); os x=output power suspend function for outx, ("1"=outx will be suspended on gin3/suspend pin (mfc="1"), "0"= always enabled (defa ult)); pllsx=determines which pllx to suspend when gin3 is programmed to be used as suspend, it suspends all the outputs associated with that pll, ("1"= suspends based on suspend pin, "0" = pll enabled and no association with susp end pin (default)); it over-ri des os x bi ts; s h=determines the function of the shutdown/oe signal pin. ("1"=global shutdown; this over-ri des oex and osx bits, "0"= ouput e nable/disable (default)) ok c=clock ok count, "0"=8 cycles, "1"=1024 cycles (default) of input clocks for revertive switchover mode: a ddress 0x1d, bit 7; address 0x1e, bits [7:3] are reserved and should be set to "0" pll0 multiplier setting config0 will be sele cted if ginx are disabled and operating in mfc mode. n0[11:0]_configx - part of pll0 m integer feedback divider values (see equation below) - for 4 configurations (default value is '0'); a0[3:0]_configx - part of pll0 m integer feedback divider values (see equation below) - for 4 configurations (default value is '0'); s sc_offset0[5:0] - spread spectrum fractional multiplier offset value. s ee spread spectrum s ettings in register address range 0x60-0x67 total multiplier value m0 = 2 * n0[11:0] + a0 + 1 + ss_offset0 * 1/64 when a0[3:0] = 0 and spread spectrum disabled, m0= 2 * n0[11:0]; when a0[3:0] > 0 and spread spectrum disabled, m0 = 2 * n0[11:0] + a0 + 1; (note : a < n-1, i.e. valid m values are 2, 4, 6, 8, 9, 10, 11, 12, 13, ..., 4095 assuming within fpfd and fvco spec);
33 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator ram (programming register) tables addr 76543210 default register hex value 7 6543210 bit # bit # (default settings) description 0x1f 00000000 00 inv1 0x20 00000000 00 odiv1_config0 0x21 00000000 00 odiv1_config1 0x22 00000000 00 odiv1_config2 0x23 00000000 00 odiv1_config3 0x24 00000000 00 0x25 00000000 00 0x26 00000000 00 0x27 00000000 00 0x28 00000000 00 0x29 00000000 00 0x2a 00000000 00 0x2b 00000000 00 0x2c 00000000 00 0x2d 00000000 00 0x2e 00000000 00 0x2f 00000000 00 0x30 00000000 00 0x31 00000000 00 0x32 00000000 00 0x33 00000000 00 0x34 01000110 46 primclk 0x35 01010101 55 src1[1:0] sm[1:0] src2[1:0] oem1[1;0] slew1[1:0] cp1[3:0]_config3 a1[3:0]_config2 n1[7:0]_config1 n1[7:0]_config3 d1[7:0]_config0 n1[11:8]_config0 cp1[3:0]_config2 d1[7:0]_config3 n1[7:0]_config0 cz1[3:0]_config3 d1[7:0]_config2 cz1[3:0]_config2 d1[7:0]_config1 cp1[3:0]_config1 cz1[3:0]_config1 rz1[3:0]_config2 src6[1:0] src5[1:0] src4[1:0] cp1[3:0]_config0 ip1[2:0]_config2 n1[11:8]_config2 a1[3:0]_config3 n1[11:8]_config3 a1[3:0]_config1 n1[11:8]_config1 cz1[3:0]_config0 rz1[3:0]_config0 rz1[3:0]_config3 rz1[3:0]_config1 src3[1:0] n1[7:0]_config2 a1[3:0]_config0 ip1[2:0]_config0 ip1[2:0]_config1 ip1[2:0]_config3 configuring output out1 inv1=output inversion for out1 ("0"= non-invert (default), "1"=invert); slew1=slew rate settings for out1 output ("00"= 2.75v/ns (default), "01"=2v/ns, "10"=1.25v/ns, "11"=0.7v/ns); oem1= output enable mode for out1 output, when used with oe1 bit and shutdown/oe pin ("0x" = tri-state (default), "10"=park low, "11"=park high); address 0x1f, bits 3, 1, 0 are reserved and should be set to "0" primclk=priority selection for input clock ("0"=xtalin/ref_in becomes primary (default), "1"=clk_in becomes primary); sm = switchover mode ("0x"=manual, "10"= auto-nonrevertive, "11"=auto-revertive (default)); bit 3 is reserved and should be set to "0". srcx[1:0]=input source selection for output dividers "qx" blocks ("00"=selected input clk, "01"=pll0, "10"=pll1, "11"=pll2); default on src1 is the selected input clock. default on src2-6 is pll0 which will be powered down. pll1 loop filter setting loop filter values for pll1 - for 4 configurations (default value is '0'); config0 will be selected if ginx are disabled and operating in mfc mode. odiv1_configx=determines which one of the 2 "qx-divider" configurations to use with, for any of the "qx-divider" block associat ed with pll1; used in mfc mode; default odiv value is "0", and use config0 of qx-divider; resistor = 0.3k ? + rz1[3:0] * 1k ? , 0.3 to 15.3kohm with 1kohm step, ("0000"=0.3kohm, "0001"=1.3kohm, "0010"=2.3kohm, ...); zero capacitor = 6pf + cz1[3:0] * 27.2pf, 6pf to 414pf with 27.2pf step, ("0000"=6pf, "0001"=33.2pf, "0010"=60.4pf", ...); pole capacitor = 1.3pf + cp1[3:0] * 0.75pf, 1.3pf to 12.55pf with 0.75pf step, ("0000"=1.3pf, "0001"=2.05pf, "0010"=2.8pf, ...) charge pump current = 5 * 2^ip1[2:0] a, 5ua to 640ua with 5, 10, 20, 40, ... binary step; pll1 input divider d1 setting pll1 d-divider values (prescaler) - for 4 configurations (default value is '0'); pll1 multiplier setting config0 will be selected if ginx are disabled and operating in mfc mode. n1[11:0]_configx - part of pll1 m integer feedback divider values (see equation below) - for 4 configurations (default value i s '0'); a1[3:0]_configx - part of pll1 m integer feedback divider values (see equation below) - for 4 configurations (default value is '0'); ssc_offset1[5:0] - spread spectrum fractional multiplier offset value. see spread spectrum settings in register address range 0x68-0x6f total multiplier value m1 = 2 * n1[11:0] + a1 + 1 + ss_offset1 * 1/64 when a1[3:0] = 0 and spread spectrum disabled, m1= 2 * n1[11:0]; when a1[3:0] > 0 and spread spectrum disabled, m1 = 2 * n1[11:0] + a1 + 1 ; (note: a < n-1, i.e. valid m values are 2, 4, 6, 8, 9, 10, 11, 12, 13, ..., 4095 assuming within fpfd and fvco spec); 0x36 0x37 0x38 00000000 00 odiv2_config0 0x39 00000000 00 odiv2_config1 0x3a 00000000 00 odiv2_config2 0x3b 00000000 00 odiv2_config3 0x3c 00000000 00 0x3d 00000000 00 0x3e 00000000 00 0x3f 00000000 00 cp2[3:0]_config2 cp2[3:0]_config1 ip2[2:0]_config0 rz2[3:0]_config1 ip2[2:0]_config1 rz2[3:0]_config0 cz2[3:0]_config1 ip2[2:0]_config3 ip2[2:0]_config2 rz2[3:0]_config3 rz2[3:0]_config2 cz2[3:0]_config0 cz2[3:0]_config2 cp2[3:0]_config0 cp2[3:0]_config3 cz2[3:0]_config3 no registers exist pll2 loop filter setting loop filter values for pll2 - for 4 configurations (default value is '0'); config0 will be selected if ginx are disabled and operating in mfc m ode. odiv2_configx=determines which one of the 2 "q x-divider" configurations to use with, for any of the "qx-divider" block associat ed with pll2; used in mfc mode; default odiv value is "0", and use config0 of qx-divider; resistor = 0.3k ? + rz2[3:0] * 1k ? , 0.3 to 15.3kohm with 1kohm step, ("0000"=0.3kohm, "0001"=1.3kohm, "0010"=2.3kohm, ...); zero capacitor = 6pf + cz2[3:0] * 27.2pf, 6pf to 414pf with 27.2pf step, ("0000"=6pf, "0001"=33.2pf, "0010"=60.4pf", ...); pole capacitor = 1.3pf + cp2[3:0] * 0.75pf, 1.3pf to 12.55pf with 0.75pf step, ("0000"=1.3pf, "0001"=2.05pf, "0010"=2.8pf, ...) charge pump current = 5 * 2^ip2[2:0] a, 5ua to 640ua with 5, 10, 20, 40, ... binary step;
34 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator ram (programming register) tables addr 76543210 register hex value 7 65 43210 0x40 00000000 00 0x41 00000000 00 0x42 00000000 00 0x43 00000000 00 0x44 00000000 00 0x45 00000000 00 0x46 00000000 00 0x47 00000000 00 0x48 00000000 00 0x49 00000000 00 0x4a 00000000 00 0x4b 00000000 00 0x4c 00 0 000 00 00 inv2 0x4d 10111011 bb 0x4e 00 0 000 00 00 0x4f 00 0 000 00 00 0x50 00 0 000 00 00 inv3 0x51 10111011 bb 0x52 00 0 000 00 00 0x53 00 0 000 00 00 bit # bit # q2[1:0]_config1 d2 [7: 0]_c onf ig1 q2[9:2]_config0 d2 [7: 0]_c onf ig2 pm2[1:0]_config1 pm2[1:0]_config0 slew2[1:0] n2[11:8]_config1 pm3[1:0]_config1 q3[1:0]_config0 pm3[1:0]_config0 q3[9:2]_config1 n2[11:8]_config3 n2[11:8]_config2 q2[9:2]_config1 oem2[1:0] q3[9:2]_config0 slew3[1:0] oem3[1:0] n2[11:8]_config0 n2 [7: 0]_c onf ig0 d2 [7: 0]_c onf ig3 n2 [7: 0]_c onf ig3 d2 [7: 0]_c onf ig0 n2 [7: 0]_c onf ig2 n2 [7: 0]_c onf ig1 q2[1:0]_config0 q3[1:0]_config1 0x54 00001100 0c inv4_1 inv4_0 0x55 10111011 bb 0x56 00 0 000 00 00 0x57 00 0 000 00 00 0x58 00001100 0c inv5_1 inv5_0 0x59 10111011 bb 0x5a 00 0 000 00 00 0x5b 00 0 000 00 00 0x5c 00000011 03 inv6 0x5d 10111011 bb 0x5e 00 0 000 00 00 0x5f 00 0 000 00 00 q5[9:2]_config1 slew6[1:0] q6[9:2]_config1 pm6[1:0]_config0 pm6[1:0]_config1 q6[1:0]_config1 q5[1:0]_config0 q6[9:2]_config0 oem6[1:0] pm5[1:0]_config1 pm5[1:0]_config0 q5[9:2]_config0 q5[1:0]_config1 q6[1:0]_config0 slew5[1:0] oem5[1:0] q4[9:2]_config0 lvl4[1:0] lvl5[1:0] q4[9:2]_config1 pm4[1:0]_config1 slew4[1:0] q4[1:0]_config0 oem4[1:0] q4[1:0]_config1 pm4[1:0]_config0 des cr ipt ion p ll 2 i npu t di vi der d2 se tti ng configuring output out3 inv3=output inversion for out3 ("0"= non-invert (default), "1"=invert); s lew3=slew rate settings for out3 output ("00"= 2.75v/ns (default), " 01"=2v/ns, "10"=1.25v/ns, " 11"=0.7v/ns); invx pmx oemx qx slewx configuring output out2 inv2=output inversion for out2 ("0"= non-invert (default), "1"=invert); s lew2=slew rate settings for out2 output ("00"= 2.75v/ns (default), " 01"=2v/ns, "10"=1.25v/ns, " 11"=0.7v/ns); inv5_1=output inversion for /out5 (" 0"= invert, " 1"=non-invert (default)); inv5_0=output inversion for out5 ("0"= invert, "1"=non-invert (default)); s lew5=slew rate settings for out5 output ("00"= 2.75v/ns (defa ult), "0 1"=2v/ns, " 10"=1.25v/ns, "11"=0.7v/ns); oe m5= output enable mode for out5 output, when used with oe5 bit and shutdown/oe pin ("0x" = tri-state (default), " 10"=park low, "11"=park high); lv l5=output io stan dard selection, ("00"=lvttl (default), "01"=lvds, "10"=lv pecl, "11"=reserved); q5[x:x]=output divider "q5" values (default value is '2') - support 2 output configurations when used in mfc mode; p m5[x:x]=divide mode, ("00"=divider disabled;"01" =divide by '1';"10"=divide by 2; "11"=divide by (q+2) (default)); (note : to enable out5, pm5 register bit values for both config0 and config1 configurations must be non-zero.) pll2 multiplier setting total multiplier value configuring output out5 inv5_1=output inversion for /out5 ("0"= invert, "1"=non-invert (default)); inv5_0=output inversion for out5 ("0"= invert, "1"= non-invert (default)); when using lvpe cl or lvds outputs, sle w5 must be set to '00'. configuring output out4 inv4_1=output inversion for /out4 ("0"= invert , "1"=non-invert (default)); inv4_0=output inversion for out4 ("0"= invert , "1"=non-invert (default));
35 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator 0x60 00000000 00 0x61 00000000 00 dith0 x2_0 0x62 00000000 00 0x63 00000000 00 0x64 00000000 00 0x65 00000000 00 0x66 00000000 00 0x67 00000000 00 0x68 00000000 00 0x69 00000000 00 dith1 x2_1 0x6a 00000000 00 0x6b 00000000 00 0x6c 00000000 00 0x6d 00000000 00 0x6e 00000000 00 0x6f 00000000 00 sd0[3:0][0] ss_offset1[5:0] sd0[3:0][11] sd0[3:0][1] sd0[3:0][10] sd0[3:0][3] sd0[3:0][2] sd0[3:0][5] sd0[3:0][6] sd1[3:0][3] nssc0[3:0] tssc0[3:0] sd1[3:0][1] tssc1[3:0] nssc1[3:0] sd1[3:0][10] sd1[3:0][9] sd1[3:0][2] sd0[3:0][4] sd1[3:0][7] sd0[3:0][7] sd0[3:0][9] ss_offset0[5:0] sd1[3:0][0] sd0[3:0][8] sd1[3:0][4] sd1[3:0][5] sd1[3:0][8] sd1[3:0][11] sd1[3:0][6] spread sprectrum settings for pll0 ss_offset0=ss fractional offset/ first sample (unsigned); tssc0=# of pfd cycles per ss cycle step, tssc="0000" for ssc off (default); nssc0=# of ss samples to use from ss memory (default is "0"); dith0=lsb dither on , ("1"=dither on, "0"=off (default)); x2_0= ? output x2, ("1"=x2, "0"=normal (default)); sd0=delta-encoded samples (unsigned); waveform start with ss_offset0, then ss_offset0+sd0[0], etc. (default is "0"); spread sprectrum settings for pll1 ss_offset1=ss fractional offset/ first sample (unsigned); tssc1=# of pfd cycles per ss cycle step, tssc="0000" for ssc off (default); nssc1=# of ss samples to use from ss memory (default is "0"); dith1=lsb dither on ? , ("1"=dither on, "0"=off (default)); x2_1= ? output x2, ("1"=x2, "0"=off (default)); sd1=delta-encoded samples (unsigned); waveform start with ss_offset1, then ss_offset1+sd1[0], etc. (default is "0"); ram (programming register) tables addr 76543210 default register hex value 7 6543210 bit # bit # (default settings) description 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80 0x81 cerr crc error in eeprom cerr = crc error bit indicator ("1`" = crc error) read-only no registers exist
36 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator package outline and package dimensions (32-pin tqfp)
37 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator recommended landing pattern, 32-pin tqfp
38 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator recommended landing pattern, 28-pin vfqfpn nl 28 pin note: all dimensions are in millimeters.
39 industrial temperature range idt5v9885c 3.3v eeprom programmable clock generator corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 clockhelp@idt.com san jose, ca 95138 fax: 408-284-2775 www.idt.com part number shipping packaging package temperature 5v9885cpfgi tubes 32-pin tqfp -40 to +85c 5v9885cpfgi8 tape and reel 32-pin tqfp -40 to +85c 5v9885cnlgi tubes 28-pin vfqfpn -40 to +85c 5v9885cnlgi8 tape and reel 28-pin vfqfpn -40 to +85c

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